View ML4818CP_313289.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

May 1997
ML4818* Phase Modulation/Soft Switching Controller
GENERAL DESCRIPTION
The ML4818 is a complete phase modulation control IC suitable for full bridge soft switching converters. Unlike conventional PWM circuits, the phase modulation technique allows for zero-voltage switching transitions and square wave drive across the transformer. The IC modulates the phases of the two sides of the bridge to control output power. The ML4818 can be operated in current mode. The delay times for the outputs are externally programmable to allow the zero-voltage switching transitions to take place. Pulse-by-pulse current limit, integrating fault detection, and soft start reset are provided. The under-voltage lockout circuit features a 6V hysteresis with a low starting current to allow off-line start up with a low power bleed resistor. A shutdown function powers down the IC, putting it into a low quiescent state.
FEATURES
s
Full bridge phase modulation zero voltage switching circuit with programmable ZV transition times Constant frequency operation to 500kHz Current mode operation Cycle-by-cycle current limiting with integrating fault detection and restart delay Precision buffered 5V reference (+1%) Four 1.5A peak current totem-pole output drivers Under-voltage lockout circuit with 6V hysteresis
s s s
s s s s
Power DIP package allows higher dissipation * Some Packages Are Obsolete)
BLOCK DIAGRAM
10 SHUTDOWN REFERENCE AND UNDER-VOLTAGE LOCKOUT INHIBIT OUTPUTS R Q 3 5 RAMP E/A OUT 0.7V S MOD VCC VREF 24
13 11 2
CLOCK RT CT OSC
20
+
+
Q
DELAY
A2 OUT
16
-
T FLIP FLOP V+ I1 T Q DELAY
VCC A1 OUT
8
INV +5V
ERROR AMP
-
17
+
9
SOFT START 3V
VCC B1 OUT
- +
R
DELAY
22
VCC R 12 RCRESET ILIM 1V Q I2 S S Q B2 OUT
DELAY
21
RDELAY GND *PINS 1, 6, 7, 15, 18, 19 AND 23 ARE GND
4
+ -
14 *
1
ML4818
PIN CONNECTION
24-Pin Power DIP
GND CT RAMP ILIM E/A OUT GND GND INV SOFT START SHUTDOWN RT RCRESET 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VREF GND B1 OUT B2 OUT VCC GND GND A1 OUT A2 OUT GND RDELAY CLOCK GND CT RAMP ILIM E/A OUT GND GND INV SOFT START SHUTDOWN RT RCRESET
1 2 3 4 5 6 7 8 9 10 11 12
24-Pin SOIC
24 23 22 21 20 19 18 17 16 15 14 13
VREF GND B1 OUT B2 OUT VCC GND GND A1 OUT A2 OUT GND RDELAY CLOCK
TOP VIEW
TOP VIEW
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 2 3
GND CT RAMP
Ground Timing capacitor for oscillator
12 13
RCRESET CLOCK RDELAY
Timing elements for Integrating fault detection and reset delay circuits Oscillator output Resistor to ground on this pin programs the amount of delay from the time an output turns off until its complementary output turns on Ground High current totem pole output A1 High current totem pole output A2 Ground and substrate Positive supply for the IC High current totem pole output B1 High current totem pole output B2 Ground Buffered output for the 5V voltage reference
Non-inverting input to main comparator. Connected to current sense resistor for current mode Current limit sense pin. Normally connected to current sense resistor
14
4 5 6,7 8 9 10
ILIM E/A OUT GND INV SOFT START
15 Output of error amplifier and input to PWM comparator Ground and substrate Inverting input to error amp Normally connected to soft start capacitor 16 17
GND A2 OUT A1 OUT
18,19 GND 20 21 VCC B2 OUT B1 OUT GND VREF
SHUTDOWN Pulling this pin low puts the IC into a power down mode and turns off all outputs. This pin is internally pulled up to VREF. RT Resistor which sets discharge current for oscillator timing capacitor
22 23 24
11
2
ML4818
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC ........................................................................... 30V Output Driver Current, Source or Sink DC ....................................................................... 0.5A Pulse (0.5 s) ........................................................ 1.5A Analog Inputs (CT, RAMP, I LIM, E/A OUT, INV, SOFT START, RCRESET) ............................... -0.3V to 6V CLOCK Output Current (RT) ....................................-5mA Error Amplifier Output Current (E/A OUT) ................ 5mA SOFT START Sink Current ..................................... 50 mA Oscillator Charging Current (CT) .............................-5mA Junction Temperature ............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (Soldering 10 Sec) ...................... 260C Thermal Resistance (JA ) Plastic Power DIP ............................................ 40C/W Plastic SOIC ..................................................... 80C/W
OPERATING CONDITIONS
Operating Temperature Range ....................... 0C to 70C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 15V, RT = 12.7k, CT = 250pF, R CLK = 3k, RDELAY = 5k, TA = Operating Temperature Range (Note 1).
PARAMETER OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation CT Discharge Current Clock Out High Clock Out Low Ramp Peak Ramp Valley Ramp Valley to Peak REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current ERROR AMPLIFIER Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain PSRR 1 < VO < 4V 12 < VCC < 25V 70 65 -40 -3 0.6 0.1 75 80 30 3 1 mV A A dB dB 10Hz to 10kHz TJ = 125C, 1000 hrs VREF = 0V -20 4.85 50 5 -50 25 TA = 25C, IO = 1mA 12V < VCC < 25V 1mA < IO < 10mA 4.95 -20 -20 5.0 2 3 .2 5.15 5.05 20 20 V mV mV mV/C V mV mV mA 0 0 line, temp. VCT = 2V 375 4.7 2.4 5.5 3.1 0 4.1 1.5 2.6 5 5 TA = 25C 12V < VCC < 25V 410 450 -0.3 0.2 525 6.3 6 0.4 525 kHz %/V % kHz mA V V V V V CONDITIONS MIN TYP. MAX UNITS
3
ML4818
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER ERROR AMPLIFIER (Continued) Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth Slew Rate PHASE MODULATOR RAMP Bias Current EA OUT Zero DC Threshold tPD, RAMP to Output tDELAY RDELAY Voltage SOFT START Charge Current Discharge Current CURRENT LIMIT/SHUTDOWN ILIM Bias Current Current Limit Threshold tPD, ILIM RCRESET Shutdown Threshold RCRESET Restart Threshold RCRESET Charging Current SHUTDOWN Threshold SHUTDOWN Input Bias Current OUTPUT Output Low Level Output High Level Rise/Fall Time UNDER-VOLTAGE LOCKOUT Start Threshold Stop Threshold SUPPLY Start Up Current ICC VCC < 15.8V VINV = 4V, VRAMP = VILIM = 0V, CL = 1nF, TA = 25C (Note 2) 3 60 4 70 mA mA 15.5 9.25 16.5 10.2 17.2 10.7 V V IOUT = 20mA IOUT = 200mA, TA = 25C IOUT = -20mA IOUT = -200mA, TA = 25C CL = 1000pF 12.0 11.0 0.1 0.7 13.5 13.0 50 75 0.4 2.8 V V V V ns VSHUTDOWN = 0 VILIM =2V, VRCRESET = 1.5V 0V < VILIM < 4V VSHUTDOWN = 0V -10 0.92 50 3.15 1.0 -400 2.0 -100 3.4 1.3 -523 2.4 -25 -1 1.02 10 1.12 ns 3.65 1.6 -1000 2.8 10 V V A V A A V VSOFT START = 4V VSOFT START = 1V -15 10 -25 20 -30 30 A mA CL = 1nF 99 4 VRAMP = 2.5V VRAMP = 0V 0.4 -1 0.6 50 200 4.3 -10 0.9 80 250 5 A V ns ns V VEA OUT = 1V VEA OUT = 5.1V IEA OUT = -0.5mA IEA OUT = 1mA 2.0 8.5 2.8 V/s 1 -0.5 5.0 3.2 -2.2 5.5 -20 6.0 0.8 mA mA V V MHz CONDITIONS MIN TYP. MAX UNITS
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: VCC must be brought above the UVLO start voltage (17.2V) before dropping to VCC = 15V to ensure start-up.
4
ML4818
FUNCTIONAL DESCRIPTION
PHASE MODULATOR Power is controlled by modulating the switching phase on sides A and B of the full H-bridge converter (Figure 1). Power is delivered to the output through the transformer secondary. The power conversion process is described by the following sequence and illustrated by the timing diagram of Figure 2: 1. A2 and B1 are high (Q1 and Q2 are on), beginning the power conversion cycle. 2. After the MOD comparator trips, B1 goes low turning off Q2. The parasitic drain-to-source capacitances of Q2 and Q4 charge to +VIN. This forces the drain-to-source voltage across Q3 to 0V. 3. B2 now goes high after tDELAY (set by RDELAY). Since the voltage across Q3 is now 0V, B2 turns Q3 on at zero voltage. 4. The CLOCK now goes high turning A2 off. During this period, Q1 and Q2 and Q4 are off. The transformer leakage current discharges the drain-tosource capacitance on Q4 until there is 0V across it. 5. A1 will remain low for a period defined by tDELAY, then it goes high. The voltage across Q4 is now 0V as A1 turns it on at zero voltage. 6. The previous sequence is now repeated with the opposite polarity on all outputs (see Figure 2). The above sequence is then repeated but with the opposite polarity on all outputs.
+VIN TB A2 B2 Q3 Q1 TA
ML4818
B Q2 A1 B1 ILIM
LLEAKAGE A TRANSFORMER Q4
RSENSE
Figure 1. Simplified diagram of Phase Modulated power Outputs.
CT
CLOCK
A2 tDELAY A1 tDELAY B1 tPD1 B2 tDELAY B tPD1 tDELAY tDELAY tDELAY tPD1
A
Figure 2. Phase Modulation control waveforms (Shaded areas indicate a power cycle).
5
ML4818
The ML4818 can also be used in current mode by sensing load current on the RAMP input (pin 3). The four output delay timers are programmed via an external RDELAY resistor as shown below. This resistor value should be no less than 1k. Expressing RDELAY in k the delay, in ns is: TDELAY = 33 x RDELAY + 45 (1)
ISET 11 RT 1.7V 2 CT 5.5mA Q1 ISET 5V CLOCK OUT 13 250 5V
+ -
The ML4818 contains special logic circuits to provide for voltage mode feed-forward and lock out long pulses into the internal logic. This prevents instability from occuring when the Comparator trips in voltage mode. Figure 5. Ocillator Block Diagram
MOD OUTPUT RAMP S Q OSC R QR 3
For frequencies of less than 500kHz, oscillator frequency can be set by using the following formulae: fOSC = 1 0.52 CT R T + 500 CT (2)
Figure 3. Voltage Feed-Forward Circuit. The collector of QR in figure 3 is high only during a power cycle. When the power cycle terminates, RAMP is pulled low. In voltage mode operation, a capacitor is connected from RAMP to GND with a resistor from RAMP to VIN to provide input voltage feed forward. OSCILLATOR The ML4818 oscillator charges the external capacitor, C T, with a current (ISET) equal to 5/RT. When the CT voltage reaches the upper threshold (Ramp Peak), the comparator changes state, turning on the current sink which discharges CT to the lower threshold (Ramp Valley). The CT pin is clamped to Ramp Valley by Q1 (Figure 5) to prevent inaccuracy due to undershoot on CT. To use the CLOCK output for driving external synchronization circuitry, a pull-down resistor is required from CLOCK to GND.
ERROR AMPLIFIER The ML4818 error amplifier is a 2.5MHz bandwidth, 8.5V/s slew rate op-amp with provision for limiting the positive output voltage swing (output inhibit line) to implement the soft start function. The error amplifier output source current is limited to 4.5mA.
CLOCK
RAMP PEAK CT RAMP VALLEY TC TD
Figure 4. Ocillator Timing Diagram
6
ML4818
VCC 120 100 80 GAIN 60 40 45 20 0 0 100 1k 10k 100k FREQUENCY 1M 0 10M GAIN PHASE 90 135 PHASE (Degrees) Q2 180 VCC
OUT
Q1 POWER GND
Figure 6. Error Amplifier Open-Loop Gain and Phase vs. Frequency.
7 6
SATURATION DROP (V)
Figure 7. Power Driver Simplified Schematic.
5 4 3 2 SINK 1 0
OUTPUT VOLTAGE (V)
15
10
10nF 10nF 1nF
SOURCE
5
1nF
100 tF
200 (ns)
~ ~
100
200 tR
0
0.2
0.4
0.6 0.8 1.0 1.2 OUTPUT CURRENT (A)
1.4
Figure 8. Output Drive Saturation Voltage vs. Output Current.
Figure 9. Output Rise/Fall Time.
OUTPUT DRIVER STAGE The ML4818 has four high current high speed totem pole output drivers each capable of 1.5A peak output, designed to quickly switch the gates of capacitive loads, such as power MOSFET transistors. Figure 8 illustrates the saturation characteristics of the ouput drive transistors shown in Figure 7. Typical rise and fall time characteristics of the output drivers are illustrated with capacitive loads of 1nF and 10nF in Figure 9.
7
ML4818
CURRENT LIMIT, FAULT DETECTION AND SOFT START Current limit is implemented when the current sensed on ILIM reaches the 1V limit. At this point, the PWM cycle is terminated. The flip flop (Figure 10) turns on the current source to charge CRST and remains on for the duration of the clock period. When CRST has charged to 3.4V, a soft start reset occurs. The number of times the PWM cycle is terminated due to over-current is "remembered" on CRST. Over time, CRST is discharged by RRST providing a measure of "forgetting" when the over-current condition no longer occurs. This integrating fault detection is useful in differentiation between short circuit and load surge conditions. Since the per cycle charge on RCRESET is proportional to how early in the power cycle the over-current occurs, a reset will occur more quickly under output short circuit conditions (Figures 11a and 11b) than during a load surge (Figures 11c and 11d). When the soft start reset occurs, the output is inhibited and the soft start capacitor is discharged. The output will remain off until CRST discharges to 1.3V through RRST, providing a reset delay. When the IC restarts, the error amplifier output voltage is limited to the voltage at SOFT START, thus limiting the duty cycle.
V+ ISWITCH I1 9 CSS SOFT START
TERMINATE PWM CYCLE 4 ILIM 1V
+ -
S V+
R1 RSENSE
C1
Q
I2 12 RRST CRST 3.4V 1.3V
R CLOCK
RCRESET
+ -
INHIBIT OUTPUT UNDER-VOLTAGE LOCKOUT
Figure 10. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
1V V(PIN 4)
1V V(PIN 4)
3.4V V(PIN 12)
3.4V V(PIN 12)
Figure 11a, 11b. ILIMIT and Resulting RCRESET Waveforms During Short Circuit.
Figure 11c, 11d. ILIMIT and Resulting RCRESET Waveforms During Load Surge.
8
ML4818
UNDER-VOLTAGE LOCKOUT On power up, when VCC is below 16V, the IC draws very little current (1.1mA typ.) and VREF is disabled. When VCC rises above 16V, the IC becomes active and VREF is enabled and will stay in that condition until VCC falls below 10.2V. (see Figure 12).
INHIBIT OUTPUTS 0.555"
1 2 3
24 23 22 21 20 19 18 17 16 15 14 13 I I
- +
4V TO LOGIC CIRCUITS 5V VREF 24
4 5
POWER DOWN
I
6 7 8 9
9V VCC
+ -
INTERNAL BIAS
I
10 11 12
20
Figure 12. Under-Voltage Lockout and Reference Circuits.
70 68 66 SUPPLY CURRENT (mA) 64 62 60 58 56 54 52 50 -75
Figure 14. PC Board Copper Area Used as a Heat Sink.
50
40
30
20
-25 25 75 125 175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
TEMPERATURE
I : HEAT SINK DIMENSION (INCHES)
Figure 13. Supply Current vs. Temperature (C).
Figure 15. JA as a Function of I (see figure 15).
THERMAL INFORMATION The ML4818 is offered in a Power DIP package. This package features improved thermal conduction through the leadframe. Much of the heat is conducted through the center 4 grounded leads. Thermal dissipation can be improved with this package by using copper area on the board to function as a heat sink. Increasing this area can reduce the JA (see figures 14 and 15), increasing the power handling capability of the package. Additional improvement may be obtained by using an external heat sink (available from Staver).
APPLICATIONS
The application circuit shown in Figure 16 features the ML4818 in a primary-side controlled voltage mode application with voltage feed-forward. Input voltage is rectified 120VAC (nominal). Feed-forward is provided by the RAMP pin via the resistor connected to the high voltage input. Current is sensed through sense transformer T4.
9
2 x IN5248 10T
4 21 80T 39 1/4W 1T T4 T1 45T 20 19 18 17 16 1N4148 7.5k, 1/4W T2 5.1, 1/4W 10T 15 14 13 5 6 7 8 9 10 11 12
220pF
100k
1N5818
470pF
1N5818
SCHOTTKY DIODE
15H + 100F 25V VCC 5.1, 1/4W IRF840 T3 10T
0.33F 630V 4T 4T
2 x IN5248
1N5818
10
82k, 1W +HV + 240k 1/4W 4 x 1N5406, 3A, 600V 5A, 250V FUSE T1 680F, 200V 240k 1/4W J1 120VAC-220VAC JUMPER + AC IN VCC 1F MUR150 4T 100F 25V + 4T 200H MUR150 680F, 200V 330k 1/4W ML4818 0.1F T2 0.01F 1kV 10T 1F IRF840 5.1, 1/4W 1 24 23 22 2 3 IRF840 5.1, 1/4W 10T 1F T3 10T 1N5818 1F + VOUT, 15V, 13A - IC2 1k,1/4W MOC8102 IRF840 1k POT 510 1/4W
ML4818
120pF
5.1k 1/4W
680pF
1000pF
470pF
100k 1/4W
1F
4.3k, 1/4W
Figure 16. Offline Full Bridge Converter.
1F
240k, 1/4W
ML4818
PHYSICAL DIMENSIONS inches (millimeters)
Package: P24N 24-Pin Narrow PDIP
1.240 - 1.260 (31.49 - 32.01) 24
PIN 1 ID
0.240 - 0.270 0.295 - 0.325 (6.09 - 6.86) (7.49 - 8.26)
0.070 MIN (1.77 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
11
ML4818
PHYSICAL DIMENSIONS inches (millimeters)
Package: S24 24-Pin SOIC
0.600 - 0.614 (15.24 - 15.60) 24
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
ORDERING INFORMATION
PART NUMBER ML4818CP ML4818CS TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE Power DIP (P24) SOIC (S24W) (Obsolete)
(c) Micro Linear 1997 Micro Linear is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS4818-01
12

▲Up To Search▲

Price & Availability of ML4818CP

	To Download ML4818CP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .